Copyright the Real-Time and Distributed Systems Group, Department of Systems and Computer Engineering Carleton University, Ottawa, Ontario, Canada. K1S 5B6 Generated by lqns, version 28.9 (UNIX) Input: template/case-01-08.in Output: template/case-01-08.out Comment: ... Convergence test value: 5.4556e-06 Number of iterations: 6 MVA solver information: Layer n step() mean stddev wait() mean stddev 1 6 75 12.5 1.5 3015 502.5 139.5 2 6 31 5.1667 0.16667 322 53.667 3.6667 Total 12 106 8.8333 1.3191 3337 278.08 94.891 Elapsed: 0:00:00 Processor identifiers and scheduling algorithms: Processor Name Type Copies Scheduling ServerP Uni 1 FCFS (V phases) UserP Inf 1 DELAY Task information: Task Name Type Copies Processor Name Pri Entry List Users ref(22) 1 UserP 0 users (2,V phases) Server serv 1 ServerP 0 service (2,V phases) Entry execution demands: Task Name Entry Name Phase 1 Phase 2 Users users 0 5 Server service 0 1 Mean number of rendezvous from entry to entry: Task Name Source Entry Target Entry Phase 1 Phase 2 Users users service 0 1 Phase type flags: All phases are stochastic. Squared coefficient of variation of execution segments: All executable segments are exponential. Open arrival rates per entry: All open arrival rates are 0. Type 1 throughput bounds: Task Name Entry Name Throughput Users users 0.2 Server service 1 Mean delay for a rendezvous: Task Name Source Entry Target Entry Phase 1 Phase 2 Users users service 0 16.9456 Service times: Task Name Entry Name Phase 1 Phase 2 Users users 0 21.9456 Server service 0 1 Service time variance (per phase) and squared coefficient of variation (over all phases): Task Name Entry Name Phase 1 Phase 2 coeff of var **2 Users users 0 1199.49 2.4906 Server service 0 1 1 Throughputs and utilizations per phase: Task Name Entry Name Throughput Phase 1 Phase 2 Total Users users 1.00248 0 22 22 Server service 1.00248 0 1.00248 1.00248 Utilization and waiting per phase for processor: ServerP Task Name Pri n Entry Name Utilization Ph1 wait Ph2 wait Server 0 1 service 1.00248 0 0 Utilization and waiting per phase for processor: UserP Task Name Pri n Entry Name Utilization Ph1 wait Ph2 wait Users 0 22 users 5.01239 0 0