Comprehensive On-Chip Traffic Generator Model for SoC Design and Synthesis
Moath Jarrah, Ameen Jarrah and Bernard Zeigler
Symposium on Theory of Modeling and Simulation (DEVS'10) (DEVS 2010)
Orlando, ON, April 11-15 2010
On-Chip traffic Modeling is a new research topic came along with NoCs design advances. On-Chip traffic varies in rate and nature based on the running application and the System on Chip components. Different traffic models have been proposed as an attempt to capture the various transactions that occur inside the network (NoC) which connects the IPs (Intellectual properties) on chip. In this research paper, recent traffic modeling paradigms will be shown and discussed. These models have been developed into traffic generators entities to emulate the traffic patterns on chip. However, none of these models (and hence traffic generators) completely captures the behaviors of different applications and the interactions between different IPs components on chip (which can alter the traffic state and rate). In this paper, I will propose a comprehensive and flexible model that is based on DEVS formalisms for modeling and simulation. Such a model could be implemented as a traffic generator that has three internal functions and input and output ports for the interactions with other IPs components such as caches, DSP units, etc.
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